| commit | e0cdaf0b19b68644b6c398be825f94327572e056 | |
| author | Aamir Bohra <aamir.bohra@intel.com> | |
| Fri, 6 Dec 2019 14:07:37 +0000 (6 19:37 +0530) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Wed, 11 Dec 2019 11:38:04 +0000 (11 11:38 +0000) | ||
| tree | f6ee82f84df13cfc0664edbbecbcdedbc61c7644 | treesnapshot (tar.gz zip) |
| parent | ddb4b0d576ce8a7a8f36ce8a8ebcfb871c11b18b | commitdiff |
soc/intel/tigerlake: add soc implementation for ETR address API
Add soc_pmc_etr_addr function definition in tigerlake SOC code.
The function is declared in common soc intel pmc driver.
Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37555
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add soc_pmc_etr_addr function definition in tigerlake SOC code.
The function is declared in common soc intel pmc driver.
Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37555
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/tigerlake/pmutil.c | diffblobblamehistory |