| commit | e01054d86eecfff846764e640eaafe58b5d5fb5d | |
| author | Christian Walter <christian.walter@9elements.com> | |
| Mon, 27 Apr 2020 16:11:51 +0000 (27 18:11 +0200) | ||
| committer | Patrick Rudolph <siro@das-labor.org> | |
| Mon, 4 May 2020 14:20:17 +0000 (4 14:20 +0000) | ||
| tree | 443a196cd883e6b8e89b947f612fdcabda56fd94 | treesnapshot (tar.gz zip) |
| parent | 066007590f5b904962f9965ace5485ddab7a89c3 | commitdiff |
soc/intel/cannonlake: Add DisableHeciRetry to config
Add DisableHeciRetry to the chip config and parse it in romstage.
Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add DisableHeciRetry to the chip config and parse it in romstage.
Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
| src/soc/intel/cannonlake/chip.h | diffblobblamehistory | |
| src/soc/intel/cannonlake/romstage/fsp_params.c | diffblobblamehistory |