| commit | db84a99011bef90c57fcbbd168c95ca6d7aceafd | |
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | |
| Tue, 24 Nov 2015 20:11:52 +0000 (24 14:11 -0600) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Sun, 24 Jan 2016 22:26:59 +0000 (24 23:26 +0100) | ||
| tree | 2f736e24db1a52c760f16db097196ee90646ed83 | treesnapshot (tar.gz zip) |
| parent | ad9a2bb0deeab41808a427e2f26420bd24ecb261 | commitdiff |
nb/amd/mct_ddr3: Properly set MR0 WR value
The existing code accidentally truncated the MSB from the MR0
WR value. While this probably had a minimal effect in reality,
it should be configured correctly for maximal system stability.
Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13147
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The existing code accidentally truncated the MSB from the MR0
WR value. While this probably had a minimal effect in reality,
it should be configured correctly for maximal system stability.
Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13147
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | diffblobblamehistory |