| commit | dabebc3716bac1dbe9445dfb2bbbbb833ee21de1 | |
| author | Dan Elkouby <streetwalkermc@gmail.com> | |
| Fri, 13 Apr 2018 15:47:10 +0000 (13 18:47 +0300) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Mon, 16 Apr 2018 08:46:30 +0000 (16 08:46 +0000) | ||
| tree | 5cc39ad5a948381b6f76a664332bde6077112ebc | treesnapshot (tar.gz zip) |
| parent | 0c024208cdd3cfdfd7689b6fcba1b5c877f550c7 | commitdiff |
nb/intel/sandybridge: support more XMP timings
Tested with a pair of GSkill F3-1866C9-8GSR.
This makes sure in particular that we honor the CMD rate requested by
the XMP profile. This memory kit needs a CMD rate of 2 to be stable at
DDR3-1600 and up, even though it passes training at 1.
Also respect requested CWL to match vendor firmware and for a potential
increase in performance. The tested kit requests a tighter value than
the per-frequency table provides and has shown to be stable using that
setting.
Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25664
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with a pair of GSkill F3-1866C9-8GSR.
This makes sure in particular that we honor the CMD rate requested by
the XMP profile. This memory kit needs a CMD rate of 2 to be stable at
DDR3-1600 and up, even though it passes training at 1.
Also respect requested CWL to match vendor firmware and for a potential
increase in performance. The tested kit requests a tighter value than
the per-frequency table provides and has shown to be stable using that
setting.
Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25664
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>