| commit | d99f9d526f9e46442b1d0158d7f881202b293183 | |
| author | Subrata Banik <subrata.banik@intel.com> | |
| Thu, 18 Jan 2018 09:43:53 +0000 (18 15:13 +0530) | ||
| committer | Subrata Banik <subrata.banik@intel.com> | |
| Wed, 24 Jan 2018 13:26:28 +0000 (24 13:26 +0000) | ||
| tree | b887b25cb6aa2d0427025044f48844962e23941c | treesnapshot (tar.gz zip) |
| parent | b7d79cddf0287a2e925d2003ef8d0cde6bbbae2a | commitdiff |
soc/intel/cannonlake: Port eMMC controller W/A from Intel Reference code
Solution: To do an additional config read to the eMMC controller
after the controller has been power gated (put to D3)
Change-Id: Ieac939c9108e84ba6c7c26b1a49aaf829d8456b7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Solution: To do an additional config read to the eMMC controller
after the controller has been power gated (put to D3)
Change-Id: Ieac939c9108e84ba6c7c26b1a49aaf829d8456b7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/soc/intel/cannonlake/acpi/scs.asl | diffblobblamehistory |