| commit | d71cfd204109b66aef0fe233e1e78e3c840fed6d | |
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | |
| Thu, 16 Jun 2016 18:14:25 +0000 (16 21:14 +0300) | ||
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | |
| Mon, 20 Jun 2016 16:43:30 +0000 (20 18:43 +0200) | ||
| tree | 39ad85048b7defc516d7c8548c24166266906d1a | treesnapshot (tar.gz zip) |
| parent | 4b86314495b17f8d944e16cfb726cd665c7d22a1 | commitdiff |
VIA C7 NANO: Fix early MTRR setting
It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.
Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.
Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/cpu/via/car/cache_as_ram.inc | diffblobblamehistory |