| commit | d2718c93815ab18bc65b866dff42d1e625fe5f2c | |
| author | Jonathan Zhang <jonzhang@fb.com> | |
| Sat, 18 Jul 2020 00:35:12 +0000 (17 17:35 -0700) | ||
| committer | Angel Pons <th3fanbus@gmail.com> | |
| Fri, 14 Aug 2020 09:08:24 +0000 (14 09:08 +0000) | ||
| tree | a6b569838724a3d33dd5f86ee89dfcc7682a45c6 | treesnapshot (tar.gz zip) |
| parent | 056f81988fdbc67af334d9dfba1e974cc577fa6b | commitdiff |
soc/intel/xeon_sp/cpx: add VT-d support
Intel CPX-SP FSP added support for VT-d through adding UPD
parameter X2apic. Based on devicetree.cb setting, enable
VT-d programming through FSP-M.
When VT-d is enabled, add DMAR ACPI table.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Intel CPX-SP FSP added support for VT-d through adding UPD
parameter X2apic. Based on devicetree.cb setting, enable
VT-d programming through FSP-M.
When VT-d is enabled, add DMAR ACPI table.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
| src/soc/intel/xeon_sp/cpx/acpi.c | diffblobblamehistory | |
| src/soc/intel/xeon_sp/cpx/chip.h | diffblobblamehistory | |
| src/soc/intel/xeon_sp/cpx/romstage.c | diffblobblamehistory |