| commit | d047927168e63004d0b4fa521b48d321af1b0ac6 | |
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | |
| Fri, 28 May 2021 14:30:02 +0000 (28 20:00 +0530) | ||
| committer | Subrata Banik <subrata.banik@intel.com> | |
| Mon, 7 Jun 2021 06:40:17 +0000 (7 06:40 +0000) | ||
| tree | 05bb492165ffde2bbb63d3445acdd21cbe94e9c3 | treesnapshot (tar.gz zip) |
| parent | b67c5edf8247f94ec7a79068156f339f1eec4ac8 | commitdiff |
soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines
The patch configures 4KB memory region window for each of the TBT DMA
remapping engine. So, the remap engines map their register set to
the respective 4KB window.
TEST=Verified boot on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55015
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch configures 4KB memory region window for each of the TBT DMA
remapping engine. So, the remap engines map their register set to
the respective 4KB window.
TEST=Verified boot on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55015
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/alderlake/romstage/fsp_params.c | diffblobblamehistory |