| commit | cb70d836ed048b81ad8047e97c9758680cc2da2d | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Mon, 11 Oct 2021 12:26:42 +0000 (11 14:26 +0200) | ||
| committer | Angel Pons <th3fanbus@gmail.com> | |
| Fri, 15 Oct 2021 13:43:05 +0000 (15 13:43 +0000) | ||
| tree | 3b94940d19c31ddb080ac9cce30cae9be3016ea8 | treesnapshot (tar.gz zip) |
| parent | adb393bdd6cd6734fa2672bd174aca4588a68016 | commitdiff |
cpu/intel/haswell: Lock PKG_CST_CONFIG_CONTROL MSR
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.
Change-Id: Ieb740aa94255cb3c23a56495c4b645d847637b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.
Change-Id: Ieb740aa94255cb3c23a56495c4b645d847637b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| src/cpu/intel/haswell/haswell_init.c | diffblobblamehistory |