| commit | ca38fbcdbfcb5024496d2577f71de06745c22aeb | |
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | |
| Thu, 25 Jul 2019 18:33:29 +0000 (26 00:03 +0530) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Fri, 9 Aug 2019 01:32:53 +0000 (9 01:32 +0000) | ||
| tree | bbd0412ece808ce427b48ac0bf31fdc552db26a8 | treesnapshot (tar.gz zip) |
| parent | dacd5b9a6ad7d4273af83d356dc869660a04662e | commitdiff |
mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Sarien.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Sarien.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| src/mainboard/google/sarien/variants/sarien/devicetree.cb | diffblobblamehistory |