| commit | c681409a8a3429c8aa8572ce18f4560fecb0c0ae | |
| author | Furquan Shaikh <furquan@google.com> | |
| Wed, 4 May 2016 23:03:36 +0000 (4 16:03 -0700) | ||
| committer | Furquan Shaikh <furquan@google.com> | |
| Fri, 6 May 2016 04:52:28 +0000 (6 06:52 +0200) | ||
| tree | a43f622d9693a2af4974fd8c4be65494f6644bc8 | treesnapshot (tar.gz zip) |
| parent | d264b46c4971f952ce88f66bb147816f5e1dc67d | commitdiff |
soc/intel/apollolake: Correct PCI write size in romstage
1. PCI command reg write should be 16-bit.
2. HPTC reg write should be 8-bit. Also, use macros instead of
hard-coded values. Currently, the macros are defined in romstage.c,
but if more P2SB macros are added, it would be good to move them to a
separate header file.
Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14613
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
1. PCI command reg write should be 16-bit.
2. HPTC reg write should be 8-bit. Also, use macros instead of
hard-coded values. Currently, the macros are defined in romstage.c,
but if more P2SB macros are added, it would be good to move them to a
separate header file.
Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14613
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
| src/soc/intel/apollolake/romstage.c | diffblobblamehistory |