soc/intel/common/block: Add common chip config block
commitc4986eb7f4eee0f305c6a6f05b45effae152062c
authorSubrata Banik <subrata.banik@intel.com>
Wed, 9 May 2018 09:25:09 +0000 (9 14:55 +0530)
committerSubrata Banik <subrata.banik@intel.com>
Wed, 6 Jun 2018 06:23:45 +0000 (6 06:23 +0000)
tree46185566d98e49bbfa60acfdedc60e1e423823d3
parentf513cebd8b966c15e3c8abcd2d0f540607ea5964
soc/intel/common/block: Add common chip config block

Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.

For now, adding i2c, gspi and lockdown configuration which will be used
by common code.

BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.

Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
52 files changed:
src/mainboard/google/chell/devicetree.cb
src/mainboard/google/eve/devicetree.cb
src/mainboard/google/fizz/devicetree.cb
src/mainboard/google/glados/devicetree.cb
src/mainboard/google/lars/devicetree.cb
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
src/mainboard/google/octopus/variants/bip/devicetree.cb
src/mainboard/google/poppy/variants/atlas/devicetree.cb
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
src/mainboard/google/poppy/variants/nami/devicetree.cb
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
src/mainboard/google/poppy/variants/soraka/devicetree.cb
src/mainboard/google/reef/variants/baseboard/devicetree.cb
src/mainboard/google/reef/variants/coral/devicetree.cb
src/mainboard/google/reef/variants/pyro/devicetree.cb
src/mainboard/google/reef/variants/sand/devicetree.cb
src/mainboard/google/reef/variants/snappy/devicetree.cb
src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
src/mainboard/google/zoombini/variants/meowth/devicetree.cb
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
src/mainboard/intel/kunimitsu/devicetree.cb
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
src/soc/intel/apollolake/Kconfig
src/soc/intel/apollolake/chip.h
src/soc/intel/apollolake/gspi.c
src/soc/intel/apollolake/i2c.c
src/soc/intel/apollolake/include/soc/soc_chip.h [new file with mode: 0644]
src/soc/intel/cannonlake/Kconfig
src/soc/intel/cannonlake/Makefile.inc
src/soc/intel/cannonlake/chip.h
src/soc/intel/cannonlake/gspi.c
src/soc/intel/cannonlake/i2c.c
src/soc/intel/cannonlake/include/soc/soc_chip.h [new file with mode: 0644]
src/soc/intel/cannonlake/lockdown.c
src/soc/intel/common/block/chip/Kconfig [new file with mode: 0644]
src/soc/intel/common/block/chip/Makefile.inc [new file with mode: 0644]
src/soc/intel/common/block/chip/chip.c [new file with mode: 0644]
src/soc/intel/common/block/include/intelblocks/chip.h [new file with mode: 0644]
src/soc/intel/skylake/Kconfig
src/soc/intel/skylake/chip.c
src/soc/intel/skylake/chip.h
src/soc/intel/skylake/chip_fsp20.c
src/soc/intel/skylake/gspi.c
src/soc/intel/skylake/i2c.c
src/soc/intel/skylake/include/soc/soc_chip.h [new file with mode: 0644]
src/soc/intel/skylake/lockdown.c