| commit | c0fd6e5ea643557254a23a7aa7b7b98f64d18737 | |
| author | Felix Held <felix-coreboot@felixheld.de> | |
| Fri, 28 May 2021 17:42:57 +0000 (28 19:42 +0200) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Fri, 11 Jun 2021 21:48:28 +0000 (11 21:48 +0000) | ||
| tree | bd50fdd2d40b904bac1f97dc75280b40f5f1c16a | treesnapshot (tar.gz zip) |
| parent | dee3bc34ad3be944390369724a46ecf01398c51a | commitdiff |
soc/amd/cezanne: remove warm reset flag code
The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1]
suggested; no matter if something was written to the register, the
NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space
always reads back as 0x7f.
[1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev
3.01
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1]
suggested; no matter if something was written to the register, the
NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space
always reads back as 0x7f.
[1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev
3.01
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>