| commit | c0bdf89ff458f84e332aa861809a23997ce1b905 | |
| author | Marc Jones <marcjones@sysproconsulting.com> | |
| Wed, 9 Dec 2020 04:55:32 +0000 (8 21:55 -0700) | ||
| committer | Marc Jones <marc@marcjonesconsulting.com> | |
| Thu, 10 Dec 2020 17:33:34 +0000 (10 17:33 +0000) | ||
| tree | e43e1d635989247c20d79e576b7c4fcfed02a217 | treesnapshot (tar.gz zip) |
| parent | 4def30d550a58ff7fa599c41cddb7ffca7e5077e | commitdiff |
soc/intel/xeon_sp/nvs: Use common global NVS
The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there
isn't anything uncommon with the soc NVS, use the Intel common NVS.
This covers the NVS cases of common code used by xeon_sp. Update
the mainboards for this change.
Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there
isn't anything uncommon with the soc NVS, use the Intel common NVS.
This covers the NVS cases of common code used by xeon_sp. Update
the mainboards for this change.
Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>