| commit | bd1fdc6e84cae1f3fa705ae229a6b8ab67f2960a | |
| author | Patrick Rudolph <siro@das-labor.org> | |
| Tue, 26 Jan 2016 07:45:21 +0000 (26 08:45 +0100) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Sat, 20 Feb 2016 04:11:37 +0000 (20 05:11 +0100) | ||
| tree | 49928772522c5a8e4c0206e7b6940548539784fe | treesnapshot (tar.gz zip) |
| parent | c3b0b7281326de836890fdb16eb92737f44b4e59 | commitdiff |
nb/intel/sandybridge/raminit: Add XMP support
Some vendors store lower frequency profiles in the regular SPD,
if the SPD contains a XMP profile. To make use of the board's and DIMM's
maximum supported DRAM frequency, try to parse the XMP profile and
use it instead.
Validate the XMP profile to make sure that the installed DIMM count
per channel is supported and the requested voltage is supported.
To reduce complexity only XMP Profile 1 is read.
Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the
default SPD.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13486
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Some vendors store lower frequency profiles in the regular SPD,
if the SPD contains a XMP profile. To make use of the board's and DIMM's
maximum supported DRAM frequency, try to parse the XMP profile and
use it instead.
Validate the XMP profile to make sure that the installed DIMM count
per channel is supported and the requested voltage is supported.
To reduce complexity only XMP Profile 1 is read.
Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the
default SPD.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13486
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
| src/device/dram/ddr3.c | diffblobblamehistory | |
| src/include/device/dram/ddr3.h | diffblobblamehistory | |
| src/northbridge/intel/sandybridge/raminit.c | diffblobblamehistory |