mediatek/mt8173: Add support for Dual DSI output
commitb927fe19549eaf045e9372f21d1ba19f65fc669f
authorJitao Shi <jitao.shi@mediatek.com>
Tue, 7 Feb 2017 00:51:01 +0000 (7 08:51 +0800)
committerJulius Werner <jwerner@chromium.org>
Tue, 25 Apr 2017 00:36:55 +0000 (25 02:36 +0200)
treecd8883c534918e037499666eea8eb4d6bcdc3a4c
parent2332adacaf9776f0eb8335c05bc0e65f9c1b2e3e
mediatek/mt8173: Add support for Dual DSI output

The MT817x display output pipeline can be configured to drive an 8-lane
MIPI/DSI panel using "dual DSI" mode.  For the "dual DSI" video data path,
the UFO block is configured to reorder the data stream into left and right
halves which are then sent by the SPLIT1 block to the DSI0 and DSI1
respectively.  The DSI0 and DSI1 outputs are then synchronously clocked at
half the nominal data rate by their respective MIPI_TX0/MIPI_TX1 phys.

Also, update the call sites in oak mainboard to avoid build breakage.

BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel

Change-Id: Id47dfd7d9e98689b54398fc8d9142336b41dc29f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19361
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
src/mainboard/google/oak/mainboard.c
src/soc/mediatek/mt8173/ddp.c
src/soc/mediatek/mt8173/dsi.c
src/soc/mediatek/mt8173/include/soc/addressmap.h
src/soc/mediatek/mt8173/include/soc/ddp.h
src/soc/mediatek/mt8173/include/soc/dsi.h