| commit | b761903b8bbcf33b1f159b7899e0970f2eac6498 | |
| author | Arthur Heymans <arthur@aheymans.xyz> | |
| Fri, 30 Apr 2021 14:11:37 +0000 (30 16:11 +0200) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Wed, 5 May 2021 11:46:43 +0000 (5 11:46 +0000) | ||
| tree | cfd3d549e0abacea4d91795be9c3382a6c1c34b2 | treesnapshot (tar.gz zip) |
| parent | c37d7b979f25332f8dec63cd70e7d8c39eef325d | commitdiff |
sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LP
The Intel Basking Ridge CRB does not have a Lynxpoint LP PCH but was
using the lp gpio code instead of the southbridge/intel/common code in
verstage.
Change-Id: I775d3dc3540fbd8a939701d873183dd016e24ba4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Intel Basking Ridge CRB does not have a Lynxpoint LP PCH but was
using the lp gpio code instead of the southbridge/intel/common code in
verstage.
Change-Id: I775d3dc3540fbd8a939701d873183dd016e24ba4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| src/southbridge/intel/common/Makefile.inc | diffblobblamehistory | |
| src/southbridge/intel/lynxpoint/Makefile.inc | diffblobblamehistory |