| commit | b0c6cffb093d82b8a24b00e1914e5195bcc0b50d | |
| author | Arthur Heymans <arthur@aheymans.xyz> | |
| Wed, 5 Sep 2018 18:39:39 +0000 (5 20:39 +0200) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Sun, 16 Sep 2018 18:57:20 +0000 (16 18:57 +0000) | ||
| tree | 7ff7d0c805cd41389399c58c3df008fd3d7f8fcf | treesnapshot (tar.gz zip) |
| parent | f2c3d8076e6ed0d8f1e2bc83d61f1930ec9d1e18 | commitdiff |
nb/intel/x4x: Don't use cached settings if CPU FSB has been changed
Using the cached CPU FSB setting can simply be wrong, in which case it won't
boot. Since the selected timings also depend on the CPU FSB, it is also best to
not use cached timings at all when a change is detected.
Tested on P5QC, swapped a 1333MHz FSB to a 800MHz FSB and it uses !fast_boot
boot path.
Change-Id: I12d91d0e892c15778409d7c00b27652ee52ca80c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Using the cached CPU FSB setting can simply be wrong, in which case it won't
boot. Since the selected timings also depend on the CPU FSB, it is also best to
not use cached timings at all when a change is detected.
Tested on P5QC, swapped a 1333MHz FSB to a 800MHz FSB and it uses !fast_boot
boot path.
Change-Id: I12d91d0e892c15778409d7c00b27652ee52ca80c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| src/northbridge/intel/x4x/raminit.c | diffblobblamehistory |