| commit | abfd165c86d8b4599523192d1847ac9afc36045f | |
| author | Ronak Kanabar <ronak.kanabar@intel.com> | |
| Thu, 18 Mar 2021 13:15:36 +0000 (18 18:45 +0530) | ||
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | |
| Tue, 23 Mar 2021 20:23:05 +0000 (23 20:23 +0000) | ||
| tree | 714fccbad9d3ddfc5dee7fb72c37ebfd0cbcd17c | treesnapshot (tar.gz zip) |
| parent | 227c64952218c7ac02548f15bb9fe1bae9ed9e02 | commitdiff |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02
The headers added are generated as per FSP v2081_02.
Previous FSP version was v2081_02.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add UPDs in Fsps.h and Fspm.h
BUG=b:180918805
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The headers added are generated as per FSP v2081_02.
Previous FSP version was v2081_02.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add UPDs in Fsps.h and Fspm.h
BUG=b:180918805
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h | diffblobblamehistory | |
| src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h | diffblobblamehistory |