| commit | a91c9196116af77a7d4c9d4a56c7b514fa961d76 | |
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | |
| Wed, 5 Aug 2020 10:46:52 +0000 (5 16:16 +0530) | ||
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | |
| Wed, 12 Aug 2020 17:39:49 +0000 (12 17:39 +0000) | ||
| tree | d1510f3466bc3905ecdb89d3e1999934a31c07ea | treesnapshot (tar.gz zip) |
| parent | 4dfdce4223e9689d230809b64178af4af60b0dd6 | commitdiff |
soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress
The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between
coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address
for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR
address is overridden with 0xfed1a000. This causes HECI transactions to
fail between FSP-M call and postcar.
BRANCH=puff
TEST=Verified sending HECI commands before and after FSP-M call on hatch.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between
coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address
for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR
address is overridden with 0xfed1a000. This causes HECI transactions to
fail between FSP-M call and postcar.
BRANCH=puff
TEST=Verified sending HECI commands before and after FSP-M call on hatch.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| src/soc/intel/cannonlake/romstage/fsp_params.c | diffblobblamehistory |