| commit | a87170b166aa20405be629c22fe6d54cc315e8e5 | |
| author | Duncan Laurie <dlaurie@chromium.org> | |
| Thu, 3 Nov 2016 17:43:14 +0000 (3 10:43 -0700) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Mon, 7 Nov 2016 19:40:48 +0000 (7 20:40 +0100) | ||
| tree | 587ddec68577c5fbf36b2681f033c1f330c3850e | treesnapshot (tar.gz zip) |
| parent | 2f3736e7aceb289d51a54679747d65eb09c1e0f1 | commitdiff |
lpss_i2c: Increase transaction timeout
When doing long transcations on an I2C bus at standard speed we saw
that long transactions could go over the 4ms limit while waiting for
it to complete on the bus.
Increase this so we can use standard speed for testing and debug in
firmware. (as there is no way to force standard speed in the kernel)
BUG=chrome-os-partner:58666
TEST=boot eve board with cr50 TPM and I2C bus at 100khz
Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17213
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When doing long transcations on an I2C bus at standard speed we saw
that long transactions could go over the 4ms limit while waiting for
it to complete on the bus.
Increase this so we can use standard speed for testing and debug in
firmware. (as there is no way to force standard speed in the kernel)
BUG=chrome-os-partner:58666
TEST=boot eve board with cr50 TPM and I2C bus at 100khz
Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17213
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| src/soc/intel/common/lpss_i2c.c | diffblobblamehistory |