| commit | a6529e789f5c460c1b378b3194e795ceb32a5171 | |
| author | Raul E Rangel <rrangel@chromium.org> | |
| Tue, 9 Feb 2021 21:38:36 +0000 (9 14:38 -0700) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Fri, 12 Feb 2021 20:42:35 +0000 (12 20:42 +0000) | ||
| tree | 1504d7b36a6ef752b0df8d8ac741c25171e8a266 | treesnapshot (tar.gz zip) |
| parent | 77ef99be22e69982a88bd77cafdb1a737fc2f185 | commitdiff |
soc/amd/cezanne: Add PCI IRQ Router definitions
These definitions were identical to picasso. The only thing I changed
was that I renamed Misc1 and Misc2 to HPET_L and HPET_H.
This change still doesn't write the PCI_IRQ register for all the PCI
devices. We need to refactor the picasso pci_gpp code first.
TEST=Boot majolica and see FCH IRQs being programmed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50451
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These definitions were identical to picasso. The only thing I changed
was that I renamed Misc1 and Misc2 to HPET_L and HPET_H.
This change still doesn't write the PCI_IRQ register for all the PCI
devices. We need to refactor the picasso pci_gpp code first.
TEST=Boot majolica and see FCH IRQs being programmed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50451
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/amd/cezanne/Kconfig | diffblobblamehistory | |
| src/soc/amd/cezanne/fch.c | diffblobblamehistory | |
| src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h | [new file with mode: 0644] | blob |