| commit | a4cad368a2996645d2ffc71425f49b246b0340ad | |
| author | Weiyi Lu <weiyi.lu@mediatek.com> | |
| Wed, 13 May 2020 02:01:14 +0000 (13 10:01 +0800) | ||
| committer | Hung-Te Lin <hungte@chromium.org> | |
| Wed, 12 Aug 2020 02:51:39 +0000 (12 02:51 +0000) | ||
| tree | b8cc9dd452fcdb4235d6bbaf49a12977f633aa7b | treesnapshot (tar.gz zip) |
| parent | 8fcc246a565b0d687c2891396719e677fe9bdf23 | commitdiff |
soc/mediatek/mt8192: Add PLL and clock init support
Add PLL and clock init code.
TEST=Boots correctly on MT8192EVB.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add PLL and clock init code.
TEST=Boots correctly on MT8192EVB.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| src/soc/mediatek/common/include/soc/pll_common.h | diffblobblamehistory | |
| src/soc/mediatek/common/pll.c | diffblobblamehistory | |
| src/soc/mediatek/mt8192/include/soc/infracfg.h | [new file with mode: 0644] | blob |
| src/soc/mediatek/mt8192/include/soc/mcucfg.h | [new file with mode: 0644] | blob |
| src/soc/mediatek/mt8192/include/soc/pll.h | [new file with mode: 0644] | blob |
| src/soc/mediatek/mt8192/pll.c | [new file with mode: 0644] | blob |