| commit | a2d4062d427d18127707306dada5e79d69bd3691 | |
| author | Naresh G Solanki <naresh.solanki@intel.com> | |
| Tue, 30 Aug 2016 15:17:13 +0000 (30 20:47 +0530) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Mon, 19 Sep 2016 19:32:22 +0000 (19 21:32 +0200) | ||
| tree | bcf9f53b1f1d74c9d04df6d42af2602ff97038b4 | treesnapshot (tar.gz zip) |
| parent | 21130c6508161ada1d28c90a4003c89afc3fd162 | commitdiff |
soc/intel/skylake: Add FSP 2.0 support in ramstage
Add FSP 2.0 support in ramstage.
Populate required Fsp Silicon Init params and configure mainboard
specific GPIOs.
Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for
pre OS screens.
Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16592
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add FSP 2.0 support in ramstage.
Populate required Fsp Silicon Init params and configure mainboard
specific GPIOs.
Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for
pre OS screens.
Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16592
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>