| commit | a08765d2871b891c8da2e8686a0db35b320c96b0 | |
| author | Furquan Shaikh <furquan@google.com> | |
| Tue, 5 Feb 2019 22:03:44 +0000 (5 14:03 -0800) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Thu, 7 Feb 2019 08:52:07 +0000 (7 08:52 +0000) | ||
| tree | a243942b77a637a7e88fdd9ac4794c8412ef5f49 | treesnapshot (tar.gz zip) |
| parent | 86d2afb86b5c76fe8da719ce7746609eb1109ff0 | commitdiff |
mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads
This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.
BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.
BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/mainboard/google/hatch/ramstage.c | diffblobblamehistory | |
| src/mainboard/google/sarien/ramstage.c | diffblobblamehistory |