| commit | a0729899d7aa2764b83ba7b8c00fe36a4bb3fb2e | |
| author | Subrata Banik <subrata.banik@intel.com> | |
| Sat, 29 Sep 2018 20:09:49 +0000 (30 01:39 +0530) | ||
| committer | Duncan Laurie <dlaurie@chromium.org> | |
| Tue, 9 Oct 2018 20:12:01 +0000 (9 20:12 +0000) | ||
| tree | fe53266c8e39afcd8a2db30006f31020a973a890 | treesnapshot (tar.gz zip) |
| parent | 50cdce95751d25e73abfe0bdd02c95029db8b7df | commitdiff |
soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices
This patch provides option for PCI IRQ mapping in both PIC and APIC mode.
TEST=Build and Boot on CNL RVP.
Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch provides option for PCI IRQ mapping in both PIC and APIC mode.
TEST=Build and Boot on CNL RVP.
Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>