| commit | 9ee02095fa1b5c532f758e287401423138687b56 | |
| author | Yidi Lin <yidi.lin@mediatek.com> | |
| Tue, 22 Sep 2020 11:56:20 +0000 (22 19:56 +0800) | ||
| committer | Hung-Te Lin <hungte@chromium.org> | |
| Wed, 18 Nov 2020 06:13:03 +0000 (18 06:13 +0000) | ||
| tree | 04ebf5e626718032b75203c35219d84066dda28b | treesnapshot (tar.gz zip) |
| parent | 9247d128390a70ab8ad5a2eba4ea73dc56a51375 | commitdiff |
mb/google/asurada: Implement board-specific regulator controls
Currently, five regulator controls are implemented for DRAM
calibration and DVFS feature.
The regulators for VCORE and VM18 are controlled by MT6359.
The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360
via EC.
BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently, five regulator controls are implemented for DRAM
calibration and DVFS feature.
The regulators for VCORE and VM18 are controlled by MT6359.
The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360
via EC.
BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| src/mainboard/google/asurada/Makefile.inc | diffblobblamehistory | |
| src/mainboard/google/asurada/regulator.c | [new file with mode: 0644] | blob |
| src/soc/mediatek/common/include/soc/regulator.h | diffblobblamehistory | |
| src/soc/mediatek/mt8192/include/soc/mt6360.h | [new file with mode: 0644] | blob |