| commit | 99289a89a3e4bb1376340a56de4ae03a1596de5d | |
| author | Subrata Banik <subrata.banik@intel.com> | |
| Tue, 22 Dec 2020 05:24:44 +0000 (22 10:54 +0530) | ||
| committer | Subrata Banik <subrata.banik@intel.com> | |
| Wed, 6 Jan 2021 02:46:43 +0000 (6 02:46 +0000) | ||
| tree | cb7787fa81d93b2904ebc04cb426c1bcda243ce3 | treesnapshot (tar.gz zip) |
| parent | 12defa9ee70e94c746f8713606e90d9f14f7eee4 | commitdiff |
soc/intel/alderlake: Update CPU microcode patch base address/size
This patch updates CPU microcode patch base address/size to FSP-S
UPD to have second microcode patch loaded successfully to enable
Mcheck flow.
This is new feature requirement for ADL as per new Mcheck initialization
flow.
BUG=b:176551651
TEST=Able to reach beyond PC6 without any MCE.
Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates CPU microcode patch base address/size to FSP-S
UPD to have second microcode patch loaded successfully to enable
Mcheck flow.
This is new feature requirement for ADL as per new Mcheck initialization
flow.
BUG=b:176551651
TEST=Able to reach beyond PC6 without any MCE.
Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/alderlake/fsp_params.c | diffblobblamehistory |