| commit | 9733f6a33687547a9a38589468a2b7b2b927461f | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Sun, 7 Jun 2020 17:23:03 +0000 (7 19:23 +0200) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Tue, 9 Jun 2020 00:32:28 +0000 (9 00:32 +0000) | ||
| tree | c13a4ee4536f88ac3b21cdd6ef1cce3d36cdfb90 | treesnapshot (tar.gz zip) |
| parent | 8ad0a4c0b88718a0b0ba4ba934ff526fe6875702 | commitdiff |
nb/intel/sandybridge: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| src/northbridge/intel/sandybridge/early_init.c | diffblobblamehistory | |
| src/northbridge/intel/sandybridge/gma.c | diffblobblamehistory | |
| src/northbridge/intel/sandybridge/romstage.c | diffblobblamehistory |