| commit | 9471d00a4f5acc5697d52e18dd74f909560a9031 | |
| author | Duncan Laurie <dlaurie@chromium.org> | |
| Thu, 2 Feb 2017 00:37:29 +0000 (1 16:37 -0800) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Sat, 4 Feb 2017 22:05:23 +0000 (4 23:05 +0100) | ||
| tree | 1c659862c0b4d25f1a4f018620d5f326031cfa9c | treesnapshot (tar.gz zip) |
| parent | 561bebfbaa55d5ab0656fbfc4866de88722d9618 | commitdiff |
google/eve: Fix DRAM DQS map
This change fixes the two sets of pins that were swapped in the
map of DQS signals from CPU to DRAM for channel 1.
Although this does not appear to have any impact to the system it
does result in different register values for DQS pin mapping that
are programmed inside FSP.
BUG=chrome-os-partner:58666
TEST=This fix was verified against the current schematic and using
FSP debug output.
Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18279
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change fixes the two sets of pins that were swapped in the
map of DQS signals from CPU to DRAM for channel 1.
Although this does not appear to have any impact to the system it
does result in different register values for DQS pin mapping that
are programmed inside FSP.
BUG=chrome-os-partner:58666
TEST=This fix was verified against the current schematic and using
FSP debug output.
Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18279
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| src/mainboard/google/eve/romstage.c | diffblobblamehistory |