soc/amd: Refactor DPTC Tablet Mode
commit9244358536aaecff29453b1693fdf202091878ef
authorTim Van Patten <timvp@google.com>
Tue, 23 Aug 2022 22:06:33 +0000 (23 16:06 -0600)
committerFelix Held <felix-coreboot@felixheld.de>
Mon, 12 Sep 2022 12:21:01 +0000 (12 12:21 +0000)
tree4b8136239b03292ffb6d6171af19ca3343a36acf
parent14bed61ba160093003613fc210b3e6b7af15d964
soc/amd: Refactor DPTC Tablet Mode

Refactor AMD DPTC tablet mode in preparation for adding low/no battery
DPTC settings.

1. Refactor and simplify acpigen_write_alib_dptc() into the following
   functions:
   - acpigen_write_alib_dptc_default()
   - acpigen_write_alib_dptc_tablet()
2. Add device tree register value dptc_tablet_mode_enable to control
   whether DPTC tablet mode is enabled for a variant.
3. Add dptc.asl to perform the necessary ACPI checking before modifying
   the DPTC settings.

BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build nipperkin
TEST=Boot skyrim

Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
14 files changed:
src/mainboard/google/zork/variants/morphius/overridetree.cb
src/soc/amd/cezanne/acpi/soc.asl
src/soc/amd/cezanne/chip.h
src/soc/amd/cezanne/root_complex.c
src/soc/amd/common/acpi/dptc.asl [new file with mode: 0644]
src/soc/amd/common/block/acpi/alib.c
src/soc/amd/common/block/include/amdblocks/alib.h
src/soc/amd/mendocino/Kconfig
src/soc/amd/mendocino/acpi/soc.asl
src/soc/amd/mendocino/chip.h
src/soc/amd/mendocino/root_complex.c
src/soc/amd/picasso/acpi/soc.asl
src/soc/amd/picasso/chip.h
src/soc/amd/picasso/root_complex.c