| commit | 91b2024bae0b35967b07eb30084c3f55fe5aaa4b | |
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | |
| Tue, 23 Feb 2021 08:33:43 +0000 (23 14:03 +0530) | ||
| committer | Werner Zeh <werner.zeh@siemens.com> | |
| Mon, 10 May 2021 06:40:37 +0000 (10 06:40 +0000) | ||
| tree | 7631928507b3f2b4f5f780ad7da351de9214399c | treesnapshot (tar.gz zip) |
| parent | 4b97a134857f98c4c0378ab0118b75b5b6a482dc | commitdiff |
soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining
We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters
for ADLRVP board.
Allowing this parameters to be filled by devicetree will allow
flexibility to update values as per board designs.
Note that both UPDs are applicable for both DDR and Lpddr memory types.
BUG=None
BRANCH=None
TEST=Build works and UPD values have been filled correctly
Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters
for ADLRVP board.
Allowing this parameters to be filled by devicetree will allow
flexibility to update values as per board designs.
Note that both UPDs are applicable for both DDR and Lpddr memory types.
BUG=None
BRANCH=None
TEST=Build works and UPD values have been filled correctly
Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| src/soc/intel/alderlake/include/soc/meminit.h | diffblobblamehistory | |
| src/soc/intel/alderlake/meminit.c | diffblobblamehistory |