| commit | 91aea428b5932c031b81a6c4921ac416f2b2c995 | |
| author | Werner Zeh <werner.zeh@siemens.com> | |
| Thu, 8 Sep 2016 05:27:29 +0000 (8 07:27 +0200) | ||
| committer | Werner Zeh <werner.zeh@siemens.com> | |
| Mon, 12 Sep 2016 04:33:53 +0000 (12 06:33 +0200) | ||
| tree | 4290e161963bfc1ca1f31d3d668b619a90ded5ca | treesnapshot (tar.gz zip) |
| parent | ba349ab12eb5c6848d7e3b727d6fcd7fbe616614 | commitdiff |
fsp_broadwell_de: Correct access to SIRQ_CNTL register
The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.
Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.
Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| src/soc/intel/fsp_broadwell_de/southcluster.c | diffblobblamehistory |