| commit | 8f537442d5d1014e333ed469d0e75a87f12cfbaf | |
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | |
| Tue, 25 Dec 2018 07:51:03 +0000 (25 13:21 +0530) | ||
| committer | Subrata Banik <subrata.banik@intel.com> | |
| Fri, 28 Dec 2018 06:39:14 +0000 (28 06:39 +0000) | ||
| tree | bc77defdf503e0aac59c1ab25718ab897fd303ed | treesnapshot (tar.gz zip) |
| parent | 3b1a42f95d3f259f18b5f211dd112d03df9f78dd | commitdiff |
mb/google/hatch: Enable console UART
This patch incorporates following changes to enable console on UART0
1. update default console number to 0
2. Enable PCI port for UART0
GPIO configuration will be done by coreboot based on correct console
number.
Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This patch incorporates following changes to enable console on UART0
1. update default console number to 0
2. Enable PCI port for UART0
GPIO configuration will be done by coreboot based on correct console
number.
Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>