| commit | 8d127846bc944fb416689ca1c93fd24f487f0bee | |
| author | Gaggery Tsai <gaggery.tsai@intel.com> | |
| Wed, 8 Jan 2020 23:35:11 +0000 (8 15:35 -0800) | ||
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | |
| Tue, 22 Dec 2020 22:21:00 +0000 (22 22:21 +0000) | ||
| tree | be107c667bbd056315ec520eaeb9e0710331e665 | treesnapshot (tar.gz zip) |
| parent | 8ba96b91dc1559c5a88bad5b4384885d3b384f11 | commitdiff |
soc/intel/cannonlake: Add Iccmax and loadlines for CML-S
Following up 3ccae2b7, this patch adds Iccmax and AC/DC
loadlines and iPL2 for CML-S CPUs. The information is from
CML EDS volume 1, doc #606599 and pdg #610244.
Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38288
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Following up 3ccae2b7, this patch adds Iccmax and AC/DC
loadlines and iPL2 for CML-S CPUs. The information is from
CML EDS volume 1, doc #606599 and pdg #610244.
Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38288
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/cannonlake/vr_config.c | diffblobblamehistory |