| commit | 8d11cdc6fa121f7f5c77b49b6e0ea689c62b3da0 | |
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | |
| Fri, 12 Mar 2021 19:46:02 +0000 (12 12:46 -0700) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Mon, 15 Mar 2021 06:03:31 +0000 (15 06:03 +0000) | ||
| tree | b033f4f825ec220c1358e36279c683884f434cd2 | treesnapshot (tar.gz zip) |
| parent | 99ab1fd13e9603cf0c8cf5a42e0b9564e05890e4 | commitdiff |
soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources
The Intel ADL BIOS specification #627270 recommends reserving the
following resources for each PCIe TBT root port:
- 42 buses
- 192 MiB Non-prefetchable memory
- 448 MiB Prefetchable memory
Add a mainboard Kconfig which will auto-select these recommended values,
in addition to PCIEXP_HOTPLUG.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icdfa2688d69c2db0f98d0523d5aba42eec1824db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51460
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel ADL BIOS specification #627270 recommends reserving the
following resources for each PCIe TBT root port:
- 42 buses
- 192 MiB Non-prefetchable memory
- 448 MiB Prefetchable memory
Add a mainboard Kconfig which will auto-select these recommended values,
in addition to PCIEXP_HOTPLUG.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icdfa2688d69c2db0f98d0523d5aba42eec1824db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51460
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/alderlake/Kconfig | diffblobblamehistory |