| commit | 8bd784eba5376eed3ad07c147096dc379ffbd187 | |
| author | Keith Hui <buurin@gmail.com> | |
| Sun, 5 Apr 2020 18:54:22 +0000 (5 14:54 -0400) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Sat, 2 May 2020 13:39:20 +0000 (2 13:39 +0000) | ||
| tree | adce8589f97b450f04aae9a7b2c768e4f2e97ff0 | treesnapshot (tar.gz zip) |
| parent | dc78275993acfc0ff4d58452e4829d65bc3a963a | commitdiff |
nb/intel/i440bx: Clean up register_values table
The table of initial i440BX register values has a bitmask that allows
preserving certain bits as they are programmed. This feature has been
unused since day one and probably will never be used. So drop it.
Drop DRB, RPS, PGPOL registers from the table as they will be
programmed during RAM init. These two reductions combined saved ~104
bytes.
Drop unneeded SDRAMC "+0".
Slightly compact a comment block.
TEST=Boot tested on asus/p2b-ls, i440bx config did not change
Change-Id: I020f616455bb671fe284993a488beb6386a03d0d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The table of initial i440BX register values has a bitmask that allows
preserving certain bits as they are programmed. This feature has been
unused since day one and probably will never be used. So drop it.
Drop DRB, RPS, PGPOL registers from the table as they will be
programmed during RAM init. These two reductions combined saved ~104
bytes.
Drop unneeded SDRAMC "+0".
Slightly compact a comment block.
TEST=Boot tested on asus/p2b-ls, i440bx config did not change
Change-Id: I020f616455bb671fe284993a488beb6386a03d0d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| src/northbridge/intel/i440bx/raminit.c | diffblobblamehistory |