| commit | 89c497b6d1aaaf0de399977279940d7c2bc00769 | |
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | |
| Thu, 28 Apr 2022 12:48:23 +0000 (28 14:48 +0200) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Tue, 17 May 2022 12:56:33 +0000 (17 12:56 +0000) | ||
| tree | 32b36ab0ffab7151ec00a1841702f938f51f2250 | treesnapshot (tar.gz zip) |
| parent | 0a635ab1e875bc96c8c00221659f6e75b4e1db14 | commitdiff |
mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
On this mainboard there are legacy PCI devices connected behind a
PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This
patch disables the unused PCI clock outputs on the XIO2001 bridge.
Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this mainboard there are legacy PCI devices connected behind a
PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This
patch disables the unused PCI clock outputs on the XIO2001 bridge.
Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c | diffblobblamehistory |