| commit | 84f428f740b7ad257729e2e68426fb5de06bde82 | |
| author | Subrata Banik <subrata.banik@intel.com> | |
| Fri, 25 Aug 2017 06:24:10 +0000 (25 11:54 +0530) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Fri, 25 Aug 2017 18:02:14 +0000 (25 18:02 +0000) | ||
| tree | dbc388162d51e74300810e79dfe7db4bab883a52 | treesnapshot (tar.gz zip) |
| parent | b51f54b518bf17a1bfb678d3d14dcf0996d882d2 | commitdiff |
soc/intel/skylake: Remove ABASE lock down programming
FSP is doing PMC ABASE lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove ABASE Lock down programming
from coreboot.
TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set.
Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP is doing PMC ABASE lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove ABASE Lock down programming
from coreboot.
TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set.
Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/soc/intel/skylake/finalize.c | diffblobblamehistory |