mb/{asrock,intel,purism}: Copy channel arrays separately
commit8216b46d7b9b88be4e31660362c4b9077670fd33
authorJacob Garber <jgarber1@ualberta.ca>
Wed, 29 May 2019 20:29:45 +0000 (29 14:29 -0600)
committerPatrick Georgi <pgeorgi@google.com>
Tue, 20 Aug 2019 15:18:10 +0000 (20 15:18 +0000)
tree95b46818db052de8fa5224ff2919b2e16ed7797f
parented316bc39cfb1f6dffcc76a245580b43ad5d0225
mb/{asrock,intel,purism}: Copy channel arrays separately

DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the
FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of
the first array and overwrite both of them at once. However, FSP_M_CONFIG
is not declared with the packed attribute, so this is not guaranteed to
work and is undefined behaviour to boot. It is cleaner and less tricky
to copy them independently. The same is true for DqsMapCpu2DramCh0 and
DqsMapCpu2DramCh1, so we change those as well.

Change-Id: Ic6bb2bd5773af24329575926dbc70e0211f29051
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 136538{8,9}, 140134{1,4}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33135
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
12 files changed:
src/mainboard/asrock/h110m/romstage.c
src/mainboard/intel/kblrvp/romstage.c
src/mainboard/intel/kblrvp/spd/spd.h
src/mainboard/intel/kblrvp/spd/spd_util.c
src/mainboard/intel/kunimitsu/romstage.c
src/mainboard/intel/kunimitsu/romstage_fsp20.c
src/mainboard/intel/kunimitsu/spd/spd.h
src/mainboard/intel/kunimitsu/spd/spd_util.c
src/mainboard/intel/saddlebrook/romstage.c
src/mainboard/intel/saddlebrook/spd/spd.h
src/mainboard/intel/saddlebrook/spd/spd_util.c
src/mainboard/purism/librem_skl/romstage.c