| commit | 7cbf391bce785cf3a815dc6a841f80611b4db6fe | |
| author | Sam Lewis <sam.vr.lewis@gmail.com> | |
| Thu, 6 Aug 2020 11:13:22 +0000 (6 21:13 +1000) | ||
| committer | Arthur Heymans <arthur@aheymans.xyz> | |
| Tue, 30 Mar 2021 11:21:49 +0000 (30 11:21 +0000) | ||
| tree | d481ad50ffedbbccc7e051c092849cb760509d9c | treesnapshot (tar.gz zip) |
| parent | 1d8d99bfd93602bbcc4f318f384a93cdad045705 | commitdiff |
mb/ti/beaglebone: Initialize DDR3
Adds initialisation of 512MB of DDR memory on the BBB to the romstage.
The parameters for the DDR peripherals are taken from U-Boot.
TEST: Booted from romstage into ramstage. Also successfully managed to
run the "ram_check" in lib.h.
Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Adds initialisation of 512MB of DDR memory on the BBB to the romstage.
The parameters for the DDR peripherals are taken from U-Boot.
TEST: Booted from romstage into ramstage. Also successfully managed to
run the "ram_check" in lib.h.
Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| src/mainboard/ti/beaglebone/Kconfig | diffblobblamehistory | |
| src/mainboard/ti/beaglebone/ddr3.h | [new file with mode: 0644] | blob |
| src/mainboard/ti/beaglebone/romstage.c | diffblobblamehistory |