| commit | 79f1c3e2a5c28e7d6b308165428c15188419d1a3 | |
| author | Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> | |
| Mon, 9 Apr 2018 18:14:42 +0000 (9 11:14 -0700) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Tue, 17 Apr 2018 10:44:47 +0000 (17 10:44 +0000) | ||
| tree | c5213c7452f594e34a1fc74dce5795f01075d60a | treesnapshot (tar.gz zip) |
| parent | f03c63ef956b53c691567e0bc3a4b61357155755 | commitdiff |
soc/intel/apollolake: Implement _PS0/_PS3 methods for PCIe root ports
Creates a common asl include file for PCIe power state methods. This
allows ports to be enabled independently.
BUG=None
BRANCH=None
TEST=None
Change-Id: I7b1cf4e14ebdfe9ecc7131dfe47c70ed7e2c3dc5
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/25532
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Creates a common asl include file for PCIe power state methods. This
allows ports to be enabled independently.
BUG=None
BRANCH=None
TEST=None
Change-Id: I7b1cf4e14ebdfe9ecc7131dfe47c70ed7e2c3dc5
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/25532
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/apollolake/acpi/pcie_port.asl | [new file with mode: 0644] | blob |