| commit | 79542fa36f919647137737ce2cf2e30042e4fe53 | |
| author | Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> | |
| Wed, 10 Mar 2021 11:50:57 +0000 (10 03:50 -0800) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Fri, 16 Apr 2021 06:50:14 +0000 (16 06:50 +0000) | ||
| tree | a8503f15568da9d506a6517cbe30adf7ca7e9b81 | treesnapshot (tar.gz zip) |
| parent | 40df8aa84bcdb13b5b7213d90eca04c3f4f6c6ac | commitdiff |
soc/amd/cezanne: Port ACPI p-state and c-state entries from picasso
Add generate_cpu_entries to device operations. Add support to
generate cpu p-state and c-state SSDT entries.
BUG=b:184151560
TEST=Dump and verify SSDT entry for CPU p-states and c-states.
Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add generate_cpu_entries to device operations. Add support to
generate cpu p-state and c-state SSDT entries.
BUG=b:184151560
TEST=Dump and verify SSDT entry for CPU p-states and c-states.
Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| src/soc/amd/cezanne/Kconfig | diffblobblamehistory | |
| src/soc/amd/cezanne/acpi.c | diffblobblamehistory | |
| src/soc/amd/cezanne/chip.c | diffblobblamehistory |