| commit | 7673f2f5e9dab30c655d2d76d76394dd750459a6 | |
| author | Lijian Zhao <lijian.zhao@intel.com> | |
| Wed, 6 Sep 2017 01:34:30 +0000 (5 18:34 -0700) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Wed, 13 Sep 2017 17:25:02 +0000 (13 17:25 +0000) | ||
| tree | 617e53a71f21ea8a32971a2ce44c10ba43107a69 | treesnapshot (tar.gz zip) |
| parent | e14d7def4f2b77e676ca8997a4e1505998b7d53d | commitdiff |
soc/intel/cannonlake: Add ramstage uart debug support
Use fixed resources for LPSS uart devices for debugging purpose.
BUG=NONE
BRANCH=NONE
TEST=Boot up with coreboot rom, without this changes, serial log will
stop print anything during PCI resourcre setup as MMIO address of UART
will be re-assigned.
Change-Id: Ib773e01d5f5358f13297400075d6920793200b88
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use fixed resources for LPSS uart devices for debugging purpose.
BUG=NONE
BRANCH=NONE
TEST=Boot up with coreboot rom, without this changes, serial log will
stop print anything during PCI resourcre setup as MMIO address of UART
will be re-assigned.
Change-Id: Ib773e01d5f5358f13297400075d6920793200b88
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/soc/intel/cannonlake/Makefile.inc | diffblobblamehistory | |
| src/soc/intel/cannonlake/uart_pch.c | [new file with mode: 0644] | blob |