complier.h: add __always_inline and use it in code base
commit75a62e76486f63f6dadb5492c205570ace81e9d5
authorAaron Durbin <adurbin@chromium.org>
Thu, 13 Sep 2018 08:10:45 +0000 (13 02:10 -0600)
committerAaron Durbin <adurbin@chromium.org>
Fri, 14 Sep 2018 08:16:37 +0000 (14 08:16 +0000)
treec3338d2ddd7b2f9f51f35432a24087fc289999fb
parentcf9ea55473cde8b9a2b9494eca452df7783376e5
complier.h: add __always_inline and use it in code base

Add a __always_inline macro that wraps __attribute__((always_inline))
and replace current users with the macro, excluding files under
src/vendorcode.

Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
28 files changed:
src/arch/arm/include/arch/hlt.h
src/arch/arm/include/smp/spinlock.h
src/arch/arm64/include/arch/hlt.h
src/arch/mips/include/arch/hlt.h
src/arch/power8/include/arch/hlt.h
src/arch/riscv/include/arch/hlt.h
src/arch/riscv/include/arch/io.h
src/arch/x86/include/arch/cpu.h
src/arch/x86/include/arch/hlt.h
src/arch/x86/include/arch/io.h
src/arch/x86/include/arch/pci_io_cfg.h
src/arch/x86/include/arch/pci_mmio_cfg.h
src/arch/x86/include/arch/smp/atomic.h
src/arch/x86/include/arch/smp/spinlock.h
src/commonlib/lz4_wrapper.c
src/cpu/amd/car/disable_cache_as_ram.c
src/cpu/amd/family_10h-family_15h/init_cpus.c
src/cpu/x86/smm/smihandler.c
src/include/compiler.h
src/include/cpu/amd/mtrr.h
src/include/cpu/x86/cache.h
src/include/cpu/x86/cr.h
src/include/cpu/x86/lapic.h
src/include/cpu/x86/msr.h
src/include/device/pci_ops.h
src/northbridge/intel/e7505/raminit.c
src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c