| commit | 752dc8e4258b708dc4a96b3d929163b1560492ae | |
| author | V Sowmya <v.sowmya@intel.com> | |
| Wed, 12 Jul 2017 08:57:09 +0000 (12 14:27 +0530) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Tue, 15 Aug 2017 23:11:16 +0000 (15 23:11 +0000) | ||
| tree | 35778030113a6f0936c7774ef4e6520050e25917 | treesnapshot (tar.gz zip) |
| parent | 1e6b980b1ec49e5ffdfb34e5373f13e82db67fb7 | commitdiff |
soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros
Rename BAR0 and BAR2 SRAM base and size macros to align with the spec.
* PMC_SRAM_BASE_0 -> SRAM_BASE_0
* PMC_SRAM_SIZE_0 -> SRAM_SIZE_0
* PMC_SRAM_BASE_1 -> SRAM_BASE_2
* PMC_SRAM_SIZE_1 -> SRAM_SIZE_2
Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20539
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename BAR0 and BAR2 SRAM base and size macros to align with the spec.
* PMC_SRAM_BASE_0 -> SRAM_BASE_0
* PMC_SRAM_SIZE_0 -> SRAM_SIZE_0
* PMC_SRAM_BASE_1 -> SRAM_BASE_2
* PMC_SRAM_SIZE_1 -> SRAM_SIZE_2
Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20539
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/apollolake/acpi/pmc_ipc.asl | diffblobblamehistory | |
| src/soc/intel/apollolake/include/soc/iomap.h | diffblobblamehistory | |
| src/soc/intel/apollolake/sram.c | diffblobblamehistory |