| commit | 710566093a504f0fecb641661c5379cad268189b | |
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | |
| Fri, 10 Jun 2016 17:35:16 +0000 (10 19:35 +0200) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Mon, 20 Jun 2016 22:11:49 +0000 (21 00:11 +0200) | ||
| tree | 3707b8c91b624e0e4dd40653d46674200eb03dc6 | treesnapshot (tar.gz zip) |
| parent | 2459f677310efdde229bab3406b2fb5d91f5ec20 | commitdiff |
riscv-spike: Move coreboot to 0x80000000 (2GiB)
This is where the RAM is (now), on RISC-V.
We need to put coreboot.rom in RAM because Spike (at the moment) only
supports loading code into the RAM, not into the boot ROM.
Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is where the RAM is (now), on RISC-V.
We need to put coreboot.rom in RAM because Spike (at the moment) only
supports loading code into the RAM, not into the boot ROM.
Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/arch/riscv/bootblock.S | diffblobblamehistory | |
| src/mainboard/emulation/spike-riscv/memlayout.ld | diffblobblamehistory |