| commit | 6b7b016b6006feb22b48a44b25fd71f1f39ad9cb | |
| author | Nico Huber <nico.h@gmx.de> | |
| Sun, 17 Nov 2019 00:45:50 +0000 (17 01:45 +0100) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Mon, 18 Nov 2019 11:51:26 +0000 (18 11:51 +0000) | ||
| tree | ec2b51076272ba80233d15c5b6db0686a6c23e3b | treesnapshot (tar.gz zip) |
| parent | 25128a79970bc9756ad33e1f1740e11321d1ff40 | commitdiff |
mb/sapphire/pureplatinumh61: Don't write BUC and beyond
The BUC register is actually only 8 bits wide and setting bit 5
(disabling GbE) is already done by generic code.
Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The BUC register is actually only 8 bits wide and setting bit 5
(disabling GbE) is already done by generic code.
Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| src/mainboard/sapphire/pureplatinumh61/early_init.c | diffblobblamehistory |