| commit | 6b284569a80f904ed7b813e302ff968bd344c40b | |
| author | Michael Niewöhner <foss@mniewoehner.de> | |
| Fri, 1 Jan 2021 20:04:37 +0000 (1 21:04 +0100) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Thu, 7 Jan 2021 08:15:04 +0000 (7 08:15 +0000) | ||
| tree | 8eebe7a02522c598e67d18da0e37c61dd34a36d6 | treesnapshot (tar.gz zip) |
| parent | 41a36a3d3ed26a540cacaa0aa39aa7e11a163760 | commitdiff |
cpu/intel: add PC10 residency counter MSR
This MSR will be used in the follow-up changes.
Change-Id: Ia6f74861502d4a9f872b2bbbab2e5f1925a14c4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49044
Reviewed-by: Lance Zhao
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This MSR will be used in the follow-up changes.
Change-Id: Ia6f74861502d4a9f872b2bbbab2e5f1925a14c4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49044
Reviewed-by: Lance Zhao
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/include/cpu/intel/msr.h | diffblobblamehistory |