| commit | 6ab7e5e0906b02b29e9634343f3e9ca722a1088e | |
| author | Patrick Rudolph <siro@das-labor.org> | |
| Wed, 31 May 2017 16:21:59 +0000 (31 18:21 +0200) | ||
| committer | Patrick Rudolph <siro@das-labor.org> | |
| Thu, 8 Jun 2017 09:40:59 +0000 (8 11:40 +0200) | ||
| tree | 0850503baa97f2531122103eaa8dd747c6e82534 | treesnapshot (tar.gz zip) |
| parent | a038835716b3a09bd3d5ab3fd7e3d48d3c3a6f13 | commitdiff |
nb/intel/sandybridge/raminit: Advertise correct frequency
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| src/northbridge/intel/sandybridge/raminit.c | diffblobblamehistory |